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IR 3/16 Encode/Decode IC Technical Data
HSDL-7001-2500 pc, tape and reel HSDL-7001#100-100pc, 50/tube
Features
* Compliant with IrDA 1.0 Physical Layer Specs * Interfaces with IrDA 1.0 Compliant IR Transceivers * Used in Conjunction with Standard 16550 UART * Transmits/Receives either 1.63 s or 3/16 Pulse Mode * Internal or External Clock Modes * Programmable Baud Rate * 2.7-5.5 V Operation * 16 Pin SOIC Package
Description
The HSDL-7001 modulates and demodulates electrical pulses from Hewlett-Packard's HSDL-1001 Infrared transceiver module and other IrDA-compliant transceivers. The HSDL-7001 can be used with a microcontroller/ microprocessor that has a serial communication interface (UART). Prior to communication, the processor selects the transmission baud rate. Serial data is then transmitted or received at the prescribed data rate. The HSDL-7001 consists of two state machines - the SIR (Serial InfraRed) Encode and SIR Decode blocks. It also contains a sequential block Clock Divide which synthesizes the required internal signal. The HSDL-7001 can be placed into the Internal Clock Mode or External Clock Mode. An external crystal is needed for the Internal Clock Mode. In applications where the external 16XCLK signal is provided, a crystal is not needed. There are two data transmission modes. Data can be transmitted and received in either a standard 3/16 modulation mode or a 1.63 s pulse mode.
Schematic
TXD
SIR ENCODE
IR_TXD
/NRST RCD SIR DECODE IR_RCV
INT_CLOCK
A0 A1 A2 16XCLK CLOCK DIVIDE
Applications
* Interfaces with IR Transceivers in: - Computer Applications: Notebook Computers Sub-notebooks Desktop PCs PDAs Printers Dongle or other RS-232 adapter - Telecom Applications: Modems Fax Machines Pagers Phones - Handheld Data Collection: Industrial Medical Transportation
PULSEMOD CLK_SEL
Pin Out
16XCLK TXD RCV A0 A1 A2 CLK_SEL GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC OSCIN OSCOUT POWERDN PULSEMOD IR_TXD IR_RCV NRST
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I/O Pinout List
Pin 1 Name 16XCLK (SIXTNCK) Type DIGIN Function Positive edge triggered input clock that is set to 16 times the data transmission baud rate. The encode and decode schemes require this signal. The signal is usually tied to a UART's BAUDOUT signal. The 16XCLK may be provided by application circuitry if BAUDOUT is not available. This signal is required when the internal clock is not used. Negative edge triggered input signal that is normally tied to the SOUT signal of the UART (serial data to be transmitted). Data is modulated and output as IR_TXD. Output signal normally tied to SIN signal of a UART (received serial data). RCV is the demodulated output of IR_RVC. Clock Multiplex Signal Clock Multiplex Signal Clock Multiplex Signal Used to activate either the Internal or External Clock. A high on this line activates the External clock (16XCLK) and a low activates the Internal clock. When the External clock is activated, the internal oscillator is put in POWERDOWN MODE. Chip Ground Active low signal used to reset the IrDA-SIR ENCODE & DECODE state machine. This signal can be tied to POR (Power On Reset) or VCC . Input from SIR optoelectronics. Input signal is a 3/16th or 1.6 s pulse which is demodulated to generate RCV output signal. This is the modulated TXD signal. A high level on this input puts the chip into the monoshot transmit mode. In this mode, when there is a negative transition on the TXD input, a rising edge on the internal transmit modulation state machine will activate a high pulse on IR_TXD for 6 crystal clock cycles. With a 3.6864 MHz crystal, this corresponds to 1.63 s. This mode cannot be used in conjunction with the 16XCLK clock. It is meant to be used with the external crystal clock. By default, this input pin is pulled to GND. A high on this input puts only the internal oscillator cell (OSCII) in POWERDOWN MODE. The cell is normally not powered down. Oscillator Output Oscillator Input Power
2
/TXD
DIGIN
3 4 5 6 7
RCV A0 A1 A2 CLK_SEL
DIGOUT DIGIN DIGIN DIGIN DIGIN
8 9 10 11 12
GND /NRST /IR_RCV IR_TXD PULSEMOD
DIGIN DIGIN DIGOUT DIGIN (with pulldown)
13
POWERDN
14 15 16
OSCOUT OSCIN VCC
DIGIN (with pulldown) ANAOUT ANAIN
Note: There are two methods of putting the internal oscillator cell in POWERDOWN MODE. Whenever the CLKSEL Pin is asserted high (External clock selected) the oscillator cell is automatically put in powerdown mode, or whenever the POWERDN Pin is asserted high.
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Table 1. Selection of Internal Clock Rate from Crystal Oscillator
Selected Clock Rate (bps) 115200 57600 19200 9600 38400 4800 2400 TEST PURPOSE A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Crystal Freq. Division Divided by 2 Divided by 4 Divided by 12 Divided by 24 Divided by 6 Divided by 48 Divided by 96 No division
Package Dimensions
-A-
16
9 -B- P 0.25 (0.010) M 8 PL. BM
16
1
8
NOTES: 1. DIMENSIONS A AND B ARE DATUMS AND T IS A DATUM SURFACE. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. CONTROLLING DIMENSION: MILLIMETER. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. MILLIMETERS MAX. MIN. 10.00 9.80 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MAX. MIN. 0.393 0.386 0.157 0.150 0.068 0.054 0.019 0.014 0.049 0.016 0.060 BSC 0.009 0.008 0.009 0.004 7 0 0.244 0.229 0.019 0.010
1 G C -T- D 16 PL. 0.25 (0.010) M T B S A S K SEATING PLANE M F R X 45 J
DIM. A B C D F G J K M PR R
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Encoding Scheme
16 CYCLES 16 CYCLES 16 CYCLES 16 CYCLES
16XCLK
TXD
IRTXD
7 CS
3 CS
The encoding scheme relies on a clock being present, which is set to 16 times the data transmission baud rate (16XCLX). The encoder sends a pulse for every space or "0" that is sent on the TXD line. On a high to low transition of the TXD line, the generation of the
pulse is delayed for 7 clock cycles of the 16XCLK before the pulse is set high for 3 clock cycles (or 3/16th of a bit time) and then subsequently pulled low. This generates a 3/16th bit time pulse centered around the bit of information ("0") that is being transmitted.
For consecutive spaces, pulses with a 1 bit time delay are generated in series. If a logic 1 (mark) is sent then the encoder does not generate a pulse.
Decoding Scheme
16 CYCLES 16 CYCLES 16 CYCLES 16 CYCLES
16XCLK
IRRXD 3 CS
RXD
The IrDA-SIR (Serial InfraRed) decoding modulation method can be thought of as a pulse stretching scheme. Every high to low transition of the IR_RXD line signifies the
arrival of a pulse. This pulse needs to be stretched to accommodate 1 bit time (or 16 16XCLK cycles). Every pulse that is received is translated into a "0" or space on the RXD line equal to 1 bit time.
Note 1: The stretched pulse must be at least 3/4 of a bit time in duration to be correctly interpreted by a UART. Note 2: It is recommended that TXD remains high when not transmitting. This ensures the LED is off and will not interfere with signal reception.
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Monoshot Operation
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CRYSTAL CLK
INT CLK (DIVBY2)
TXD
INTERNAL IRTXD OUTPUT
IRTXD (MONOSHOT)
6 CRYSTAL CYCLES
The figure above illustrates the operation of the monoshot when the internal clock is set to divide by 2 mode, i.e., when A2=0, A1=0, and A0=0. A rising edge on the internal modulation state machine (IRTXD OUTPUT), will cause the output on the IRTXD to go up for 6 crystal clock cycles.
With a 3.6864 MHz clock, this corresponds to a pulse of 1.63 s. The duration of this pulse is independent of the code A2, A1,A0 and is always 6 clock cycles of the crystal, corresponding to the monoshot operation.
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Absolute Maximum Ratings
Parameter Storage Temperature Operating Temperature Output Current Power Dissipation[1] Input/Output Voltage[2] Power Supply Voltage Electrostatic Protection Symbol TS TA IO PMAX VI/VO VCC VESD Min. -65 -40 -100 -0.5 -0.5 Max. +150 +85 100 0.46 VCC + 0.5 7.0 4000 Units C C mA W V V V
Notes: 1. Maximum power dissipation is given for Rth = 140 C/W (SO 16 Plastic). 2. All pins are protected from damage to static discharge by internal diode clamps to VCC and GND.
Switching Specifications
(VCC = 2.7 to 5.5 V, TA = -20 to +85C) Parameter Symbol [1] Propagation Delay Time tpd Output Rise Time[2] trise Output Fall Time[3] Output Capacitance on Output Pads Used for Simulation tfall COUT Min. 3.7 10 4.4 11 Typ. 7.25 16 8.35 16 Max. 80 11.6 24 11.2 26 50 Units ns ns ns pF Conditions VCC VCC VCC VCC = 5.5 V, CL = 50 pF = 2.7 V, CL = 50 pF = 5.5 V, CL = 50 pF = 2.7 V, CL = 50 pF
Notes: 1. Propagation Delay Time in the output buffer is the time taken from the input passing VCC/2 to the time of the output reaching VCC/2 with 50 pF as the output load. 2. The Output Rise Time is the time taken for the outputs (RCV, IR_TXD) to rise from 10% of the original value to 90% of the final value. 3. The Output Fall Time is the time taken for the outputs (RCV, IR_TXD) to fall from 90% of the original value to 10% of the final value.
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Recommended Operating Conditions
(VCC = 2.7 to 5.5 V, TA = -20 to +85C) Parameter Supply Voltage Input Voltage Ambient Temperature High Level Input Voltage Low Level Input Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Static Power Dissipation Dynamic Power Dissipation Static Current Consumption Dynamic Current Consumption Max Clk Frequency (16XCLK) [1] Minimum Pulse Width (IR_TXD)[2] Pulse Width on Monoshot (IR_TXD and IR_RCV) Value of Pulldown Resistor Used on POWERDOWN & PULSEMOD Input Pins Trigger Low Level Input Voltage (For /NRST Input Pin) Trigger High Level Input Voltage (For /NRST Input Pin) Symbol VCC VI TA VIH VIL VOH VOL VOH VOL PSTAT PDYN ISTAT IDYN f16XCLK tmpw tmpw RDWN VIL_TRIG VIH_TRIG 0.44 0.11 11 5.4 80 40 2 2 1630 1630 114 0.7 1.9 1.7 3.25 4.5 0.5 0.61 0.15 16.5 8.1 110 54 3 3 2 1730 256 0.9 2.00 1.9 3.60 Min. 2.7 0.0 -20 0.7 VCC 0 2.2 Typ. 5 Max. 5.5 VCC +85 VCC 0.3 VCC Units V V C V V V V V V mW mW mW mW A A mA mA MHz ns ns K V V VCC = 2.7 V VCC = 5.5 V VCC = 2.7 V VCC = 5.5 V Conditions
0.5
VCC = 2.7 V ioh = 2 mA VCC = 2.7 V iol = 2 mA VCC = 5.5 V ioh = 2 mA VCC = 5.5 V iol = 2 mA VCC = 5.5 V VCC = 2.7 V VCC = 5.5 V VCC = 2.7 V VCC = 5.5 V VCC = 2.7 V VCC = 5.5 V VCC = 2.7 V
1710 152 0.8 1.95 1.85 3.4
Notes: 1. IrDA Parameters. The Max Clk Frequency represents the maximum clock frequency to drive the HSDL-7001's internal state machine. Under normal circumstances, the clock input should not exceed 16* 115.2 Kbps or 1.8432 MHz. This product can operate at higher clock rates, but the above is the recommended rate. 2. The Minimum Pulse Width (t mpw) represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RCV pulse). As per the IrDA specifications, the minimum pulse width of the IR_TXD and IR_RCV pulses should be 3*(1/1.8432 MHz) or 1.63 s.
Application Circuits
HSDL-7001 Connection to UART
HSDL-1001 HSDL-7001 UART 16550
TXD
IR_TXD
TXD
SOUT
RCV
SIN
RCV
IR_RCV
16XCLK NRST 10 k VCC 0.1 F
BAUDOUT
HSDL-7001 Connected to Microcontroller
HSDL-1001 HSDL-7001 MICROCONTROLLER
TXD
IR_TXD
TXD
SDO
RCV
SDI
RCV
IR_RCV
15 pF OSCIN F = 3.6864 MHz 15 pF 10 M OSCOUT
A0 A1 A2 CLK_SEL PULSEMOD POWERDN
I01 I02 I03 I04 I05 I06
NRST
10 k VCC 0.1 F
NOTE: POWERDN CAN BE USED AS A BASIC CHIP SELECT. THE HSDL-7001 WILL NOT BE ABLE TO RECEIVE OR TRANSMIT DATA WHILE POWERDN IS ASSERTED.
www.hp.com/go/ir For technical assistance or the location of your nearest Hewlett-Packard sales office, distributor or representative call: Americas/Canada: 1-800-235-0312 or 408-654-8675 Far East/Australasia: Call your local HP sales office. Japan: (81 3) 3335-8152 Europe: Call your local HP sales office. Data subject to change. Copyright (c) 1999 Hewlett-Packard Co. Obsoletes 5965-5150E (11/96) 5968-7456E (8/99)

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